1. Technical Field of the Invention
This invention pertains to an improved hardware design for programmable logic arrays (PLAs). In particular, this invention tackles the problems associated with propagation delay of signals through a PLA, thereby providing enhanced performance of the PLA structure.
2. Background Art
The need for quick turn around time for generation of logic is well known. PLAs help tackle this need in that they can be easily automated in their creation. The propagation delay of signals through PLAs is a concern especially on high performance chips. One problem that can occur in PLAs with respect to its propagation delay is a particularly slow path or paths from the true/complement generator input or inputs through a product term or terms that increase the entire delay of the PLA. These slow paths can affect many of the PLA outputs, thereby producing significant signal propagation delay in many of the input-to-output transitions.
It is an object of the invention to reduce signal propagation delay through a PLA by redesigning pre-identified slow signal paths.
It is another object of the invention to provide a PLA with superior delay characteristics resulting from better placement of slow signal paths.